High-Performance Real-Time PHIL Architectures for PMSM Emulation in Electric Drive Systems

Power hardware-in-the-loop (PHIL) systems have emerged as a flexible and cost-effective alternative for testing variable-speed drives (VSDs) by replacing physical electrical machines with emulators. This approach improves laboratory safety, eliminates mechanical rotating parts, and facilitates reproducible, accelerated testing campaigns. This research provides an in-depth review of Electrical Machine Emulators (EMEs) and proposes a unified four-block architecture consisting of a coupling network, power converter, controller, and machine model. Based on this framework, the thesis establishes the foundational baselines for the PHIL emulation of permanent-magnet synchronous machines (PMSMs). Initial focus is placed on PMSM modeling and the characterization of the device under test (DUT), covering both converter topology and control systems. The core PHIL concepts are analyzed by comparing scenarios where the coupling inductance matches the desired synchronous inductance against those where it does not, explicitly formulating the positive or negative virtual inductance the EME must reproduce. The investigation explores several architectural variations, including the use of L-filter versus LCL-filter interfaces, the distinction between full-bandwidth and fundamental-frequency emulation, the impact of controlling voltage versus current within the EME, and the effects of parameter mismatch between the DUT-side coupling inductance and the target PMSM synchronous inductance. A significant portion of the work is dedicated to current-ripple reproduction, clarifying the feasibility of accurate ripple emulation and tracing how ripple flows through the proposed architectures. Experimental results were gathered on a standardized PHIL platform using a fixed VSD, constant switching frequency, and identical machine-model computations. These results were complemented by a HIL-based validation of the full-bandwidth emulation architecture using an LCL coupling network. The experimental campaigns characterize each architecture through defined figures of merit, enabling a quantitative comparison that serves as a practical design guideline for future PHIL-based PMSM emulation.