A new architecture of subranging ADC is proposed. Against a little increase of the number of comparators than a classical subranging architecture, the substitution of the DAC and summing node brings to a reduction of total conversion time, approaching it to an ADC flash behavior.
Leccese, F. (2007). New subranging adc architecture for telecommunication systems. In INTELEC 2007 (pp.807-810) [10.1109/INTLEC.2007.4448894].