In medical ultrasound scanning applications PMUT (Piezo Micromachined Ultrasound transducers) need to be assembled along with the ASIC devices that drive the PMUT devices in transmission and receive the reflected ultrasound signal. To produce a sufficiently high resolution image, a large number of interconnections are required between the PMUT device and the companion ASICs (Application Specific Integrated Circuit) which is done using Cu pillar technology. This integration of Ultrasound Transducers using wafer level bonding between the traducer and the ASIC wafer has already been demonstrated [1]. This process suffers from the problem of yield if a non functioning transducer is bonded to a functioning ASIC or vice versa, and it also requires the ASIC die to be the same dimensions of the traducer die. In this article we will present a solution where known good ASIC die are assembled in a FOWLP (Fan Out wafer level Package) with known good PMUT device assembled using Cu pillar technology allowing for the optimisation of the ASIC for size/yield while still maintain the performance of the transducer required. Verification of the assembly flow has been done using a dummy die to ensure that the fully assembled FOWLP is practicable.

Giusti, D., Quaglia, F., Rahul, D., Rao, V.S., Savoia, A., Shaw, M., et al. (2022). Co-packaging of PMUT array with FOWLP ASIC's. In Proceedings of the 24th Electronics Packaging Technology Conference, EPTC 2022 (pp.280-285). Institute of Electrical and Electronics Engineers Inc. [10.1109/EPTC56328.2022.10013202].

Co-packaging of PMUT array with FOWLP ASIC's

Savoia A.;
2022-01-01

Abstract

In medical ultrasound scanning applications PMUT (Piezo Micromachined Ultrasound transducers) need to be assembled along with the ASIC devices that drive the PMUT devices in transmission and receive the reflected ultrasound signal. To produce a sufficiently high resolution image, a large number of interconnections are required between the PMUT device and the companion ASICs (Application Specific Integrated Circuit) which is done using Cu pillar technology. This integration of Ultrasound Transducers using wafer level bonding between the traducer and the ASIC wafer has already been demonstrated [1]. This process suffers from the problem of yield if a non functioning transducer is bonded to a functioning ASIC or vice versa, and it also requires the ASIC die to be the same dimensions of the traducer die. In this article we will present a solution where known good ASIC die are assembled in a FOWLP (Fan Out wafer level Package) with known good PMUT device assembled using Cu pillar technology allowing for the optimisation of the ASIC for size/yield while still maintain the performance of the transducer required. Verification of the assembly flow has been done using a dummy die to ensure that the fully assembled FOWLP is practicable.
2022
979-8-3503-9885-4
Giusti, D., Quaglia, F., Rahul, D., Rao, V.S., Savoia, A., Shaw, M., et al. (2022). Co-packaging of PMUT array with FOWLP ASIC's. In Proceedings of the 24th Electronics Packaging Technology Conference, EPTC 2022 (pp.280-285). Institute of Electrical and Electronics Engineers Inc. [10.1109/EPTC56328.2022.10013202].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11590/434280
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