This paper presents a novel Space Vector Modulation (SVM) strategy for the three-phase 7-level Multiplexed Converter (3Φ7L MLMXC) in high-power AC applications. The main idea of the proposed SVM is to use the dq-coordinate to rapidly find the switching triangle enclosing the reference vector in the 7-L space vector diagram. All available switching sequences and vector duty cycles are pre-allocated on look-up tables to speed up the algorithm in embedded digital platforms. All the steps of the proposed SVM strategy are implemented in one half sector that can be implemented with a minimum computational burden. The proposed algorithm provides high quality waveforms and avoids the intrinsic forbidden states, preventing the catastrophic failure of the power conversion system. The algorithm has been implemented into a field-programmable gate array (FPGA) and tested using the Hardware-In-the-Loop (HIL) equipment. This paper presents results under different operating conditions to verify the proposed SVM strategy.
Bembich, P.P., Di Benedetto, M., Lidozzi, A., Solero, L., Meynard, T.A. (2023). Space Vector Modulation Strategy for a Three-Phase 7-Level Multiplexed Converter. In 2023 IEEE Energy Conversion Congress and Exposition, ECCE 2023 (pp.2802-2808). Institute of Electrical and Electronics Engineers Inc. [10.1109/ECCE53617.2023.10362632].
Space Vector Modulation Strategy for a Three-Phase 7-Level Multiplexed Converter
Bembich P. P.;Di Benedetto M.;Lidozzi A.;Solero L.;
2023-01-01
Abstract
This paper presents a novel Space Vector Modulation (SVM) strategy for the three-phase 7-level Multiplexed Converter (3Φ7L MLMXC) in high-power AC applications. The main idea of the proposed SVM is to use the dq-coordinate to rapidly find the switching triangle enclosing the reference vector in the 7-L space vector diagram. All available switching sequences and vector duty cycles are pre-allocated on look-up tables to speed up the algorithm in embedded digital platforms. All the steps of the proposed SVM strategy are implemented in one half sector that can be implemented with a minimum computational burden. The proposed algorithm provides high quality waveforms and avoids the intrinsic forbidden states, preventing the catastrophic failure of the power conversion system. The algorithm has been implemented into a field-programmable gate array (FPGA) and tested using the Hardware-In-the-Loop (HIL) equipment. This paper presents results under different operating conditions to verify the proposed SVM strategy.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
