Estimation of the collapse (Vcol) and snapback (Vsb) voltages of Capacitive Micromachined Ultrasonic Transducers (CMUTs) is usually performed by extracting C-V curves from low frequency impedance measurements at different bias points. However, impedance analysis in several bias conditions is time-consuming, making this technique unsuitable for wafer-level testing. Additionally, prolonged exposure to high electric fields may lead to charge injection and trapping phenomena in the CMUT in-cavity insulation layers. This paper proposes an adjustment to the conventional impedance analysis technique aimed at enhancing estimation accuracy and introduces a novel technique for fast C-V assessment enabling rapid wafer-level characterization. Results from both techniques are compared, demonstrating the validity of the proposed approaches.
Khan, M.U., La Mura, M., Saccher, M., Van Schaijk, R., Dekker, R., Savoia, A.S. (2024). Fast and Accurate Estimation of Collapse and Snapback Voltages of CMUTs. In IEEE Ultrasonics, Ferroelectrics, and Frequency Control Joint Symposium, UFFC-JS 2024 - Proceedings (pp.1-4). 345 E 47TH ST, NEW YORK, NY 10017 USA : Institute of Electrical and Electronics Engineers Inc. [10.1109/UFFC-JS60046.2024.10793933].
Fast and Accurate Estimation of Collapse and Snapback Voltages of CMUTs
Khan M. U.;La Mura M.;Savoia A. S.
2024-01-01
Abstract
Estimation of the collapse (Vcol) and snapback (Vsb) voltages of Capacitive Micromachined Ultrasonic Transducers (CMUTs) is usually performed by extracting C-V curves from low frequency impedance measurements at different bias points. However, impedance analysis in several bias conditions is time-consuming, making this technique unsuitable for wafer-level testing. Additionally, prolonged exposure to high electric fields may lead to charge injection and trapping phenomena in the CMUT in-cavity insulation layers. This paper proposes an adjustment to the conventional impedance analysis technique aimed at enhancing estimation accuracy and introduces a novel technique for fast C-V assessment enabling rapid wafer-level characterization. Results from both techniques are compared, demonstrating the validity of the proposed approaches.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


